• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Integrated circuit comprising a silicon-on-insulator substrate (10) having a semiconductor film (20n, p) located above a buried insulating layer (30), at least one single programming type memory cell having a MOS capacitor (C) having a first electrode region (E1) including an at least partially silicided gate region (G) (ZSE1) and flanked by an insulating lateral region (CI1, CI2, CI4 and CI5), a dielectric layer ( OX) located between the gate region (G) and the semiconductor film (20n and 20p), and a second electrode region (E2) including a silicide region (ZSE2) of the semiconductor film located adjacent to said insulating lateral region ( CI1, CI2, CI4 and CI5), and extending at least partially under the dielectric layer (OX).
    公开号:FR3036530A1
    申请号:FR1554457
    申请日:2015-05-19
    公开日:2016-11-25
    发明作者:Stephane Denorme；Philippe Candelier
    申请人:STMicroelectronics SA；
    IPC主号:
    专利说明:

    [0001] 1 Method for producing memory cells of the single programming type comprising MOS capacitors and corresponding integrated circuit Modes of implementation and embodiment of the invention relate to non-volatile memory cells of the single programming type, known to man of the trade under the acronym Anglosaxon "OTP" ("One Time Programmable") and more particularly the MOS capacitors of such memory cells. A memory cell of the single programming type generally comprises a capacitor, for example of the MOS type, having a dielectric layer between its two electrodes and operates as an anti-fuse whose state is irreversibly modified, for example by breakdown of the dielectric layer, by applying a high programming voltage to the memory cell, so that the memory cell goes from a non-conductive state to a conductive state, which amounts to changing its resistance. In advanced CMOS technologies, transistors, for example planar CMOS transistors, FinFETs or transistors made on a substrate on an insulator, for example by a substrate of the FDSOI ("Fully Depleted") type, are formed by epitaxial growth of source and drain regions. Silicon-On-Insulator "). A silicon on insulator substrate comprises a semiconductor film, for example silicon or silicon alloy, such as a silicon-germanium alloy, located above a buried insulating layer, commonly referred to by the acronym anglosaxon "BOX" ("Buried OXide") itself located above a carrier substrate, for example a semiconductor box.
    [0002] In an FDSOI substrate, the silicon film is totally deserted (the semiconductor material is intrinsic) and has a particularly low thickness of the order of a few nanometers. The use of raised drain source regions makes it possible to solve reliability problems, such as the hot carrier reliability (HCI: Hot Carrier Injection) of the transistors as well as the problem of the mechanical strength of the metal silicide. In general, the MOS capacitors of the OTP memory cells are made in conjunction with the MOS transistors using similar process steps. However, these raised epitaxial regions have no impact on the performance of the MOS capacitors, as regards the breakdown of the dielectric layer, as regards the reading voltage, the leakage of the capacitor or else others of these electrical characteristics. Thus, according to an implementation and embodiment, it is proposed to improve, in particular at the reading level, the performance of the MOS capacitors made jointly with MOS transistors whose formation of the source and drain regions 15 comprises an epitaxy of a semiconductor material from the same SOI substrate, in particular FDSOI. According to one aspect, there is provided a method, comprising an embodiment of at least one single programming type memory cell, comprising an embodiment of a MOS capacitor in and / or on a semiconductor film of a silicon-type substrate. on insulator including a formation of a first electrode region by at least partial siliciding of an insulated gate region resting on the semiconductor film and flanked by an insulating lateral region, and forming a second region of silicide electrode of a region of the semiconductor film next to said insulative side region without prior epitaxy of semiconductor material on said region of the semiconductor film. Thus, by directly siliciding the semiconductor film, the silicided regions can be diffused under the gate dielectric which reduces the read access resistance and makes it possible to apply a lower reading voltage.
    [0003] The breakdown performance of the dielectric is also improved (reduced breakdown voltage and / or decreased breakdown time). Whether or not the silicided regions join under the dielectric layer depends on the gate length. On the other hand, even greater efficiency is achieved when the gate region is fully silicided. The method may further comprise an embodiment of at least one MOS transistor whose formation of the source and drain regions comprises an epitaxy of a semiconductor material on the semiconductor film. In this case the formation of said second electrode region comprises a protection of said semiconductor film zone by at least one insulating layer during said epitaxial growth of the source and drain regions.
    [0004] The substrate may be of the totally deserted silicon on insulator type. In another aspect, there is provided an integrated circuit comprising a silicon on insulator substrate having a semiconductor film located above a buried insulating layer, at least one single programming type memory cell having a MOS capacitor having a first electrode region including an at least partially silicided gate region and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicide area. semiconductor film located adjacent said insulative side region and extending at least partially under the dielectric layer.
    [0005] Advantageously, said silicided zone of the semiconductor film can extend completely under said dielectric layer. The integrated circuit may further include at least one MOS transistor having raised regions of source and drain.
    [0006] The substrate may for example be of the totally deserted silicon on insulator type. Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and embodiments, in no way limiting, and the attached drawings in which: FIGS. 1 to 11 schematically illustrate modes of implementation and realization of the invention. In FIG. 1, the reference IC designates an integrated circuit in which it is desired to make a MOS capacitor C together with a TN NMOS transistor and a PMOS transistor TP on the same totally deserted silicon-on-insulator semiconductor substrate 10. This substrate comprises here a 20n and 20p semiconductor thin film typically having a thickness of the order of some 15 nanometers and resting on a buried oxide layer 30 commonly referred to by those skilled in the art under the name of "BOX" Anglo-Saxon. This buried oxide layer 30 is typically made of silicon dioxide and rests itself on a carrier substrate 40 which can be formed by boxes.
    [0007] The substrate 10 further comprises insulating regions including, for example, shallow trenches 50 (STI: "Shallow Trench Isolation") which mutually isolate the NMOS transistor TN, the PMOS transistor TP and the capacitor C. Depending on the conductivity type of the NMOS or PMOS transistors, the semiconductor thin film may consist of a hetero-material and may be doped with N-type or P-type dopants or even undoped. The capacitor C rests here on a thin film of the same type as that used for the NMOS transistors. Of course, it would also be possible for it to rest on a thin film of the same type as that used for PMOS transistors. As illustrated in FIG. 1, G gate regions isolated from the substrate 10 are firstly formed above the substrate 10 in a conventional manner and known per se by a dielectric layer OX 3036530 5 advantageously comprising a material with a high dielectric constant K (high-K materials). The gate region G comprises for example above the OX layer, a poly-silicon layer.
    [0008] Typically, this is a gate first architecture since the gate region G is formed prior to the realization of the raised source and drain regions. A hard mask layer HM, for example silicon nitride, protects each gate region G from the later steps which will now be described. Firstly, a conformal deposition of a first layer 1 comprising a first insulating material is produced, for example by an atomic layer deposition commonly known to those skilled in the art under the acronym "ALD" ("Atomic Layer Deposition"). ").
    [0009] This first insulating material may for example be silicon nitride and its thickness is for example of the order of 10 nm. For the realization of the raised source and drain regions of the NMOS transistor TN, the transistor TP and the capacitor C are protected by a block of resin RP1 conventionally formed by photolithography, as illustrated in FIG. 2. Next, FIG. ) a first anisotropic etching of the first layer 1 so as to discover the semiconductor film 20n and form a first insulating layer CI1 on the edges of the insulated gate region G of the NMOS transistor TN. This selective anisotropic etching up to the silicon layer may be a dry etching of the type reactive ion etching ("RIE: Reactive-Ion Etching") well known to those skilled in the art. The thickness of the first insulating layer CI1 is for example equal to 6 nm.
    [0010] The resin block RP1 is then removed and, for example, a pre-epitaxial cleaning treatment of the thin film 20n is carried out on either side of the gate region G of the NMOS transistor TN. Then, as illustrated in FIG. 3, an epitaxy of an N-doped semiconductor material, for example SiCP, is carried out on the semiconductor film 20n so as to form on each side of the gate region G of the NMOS transistor. raised source and drain regions RSn based on the first insulating layer CI1. The realization of the raised source and drain regions for the PMOS transistor TP is then prepared (FIG. Firstly, on the structure of FIG. 3, a conformal deposition of a second protective layer 2 comprising a second insulating material, for example by a deposit of the ALD type, is carried out. This second insulating material may for example be silicon dioxide SiO 2, and the thickness of layer 2 may be of the order of 7 nm. Two resin blocks RP2 are then photolithographed above the NMOS transistor and the capacitor C. A second anisotropic etching of the second layer 2 and the first layer 1 is then carried out in the region of the PMOS transistor TP so as to discover the semiconductor film 20p and forming a second insulating layer Cl2 on the flanks of the first insulating layer CI1 based on the isolated gate region G of the PMOS transistor TP.
    [0011] The thickness of the second insulating layer Cl2 is for example of the order of 3 nm. Following a withdrawal of the resin blocks RP2, an epitaxy of a P-doped semiconductor material, for example SiGeB, is carried out. on the semiconductor film 20p to form raised source and drain regions RSp on either side of the gate region G of the PMOS transistor TP and resting on the second insulating layer Cl2, as illustrated in FIG. 5 It should be noted that the source and drain regions RSn of the NMOS transistor TN and the region of the semiconductor film located on either side of the gate region G of the capacitor C are respectively protected by the second layer 2 of protection and by the layers 1 and 2, during the epitaxy of the source and drain regions of the PMOS transistor TP.
    [0012] Thus, after removal of the protective layers 1 and 2 by a RIE type etching step, a TN NMOS transistor and a PMOS TP transistor having raised source and drain regions are obtained. On the other hand, as illustrated in FIG. 5, the capacitor C does not have raised regions epitaxially on either side of its gate region G. Then, a third protective layer is deposited on the structure of FIG. 3, for example silicon dioxide (Figure 6). A third anisotropic etching of the third layer 3 is then carried out so as to form a third insulating layer CI3 resting on the flanks of the second insulating layer Cl2 (FIG. 7). The hard mask HM silicon nitride is removed by wet etching. Surface cleaning is then carried out using hydrofluoric acid to obtain the structure as illustrated in FIG. 8. Before proceeding to the siliciding step, the entire integrated circuit is covered with a bilayer 4 (FIG. nitride oxide for example) known to those skilled in the art by the acronym "SiProt" ("Silicon Protection") (FIG. 9). This bilayer serves to protect the areas (not shown in the figures) of the integrated circuit that must not be silicided. The bilayer 4,5 is then etched so as to discover the regions to be silicided and form a fifth insulating layer CI5 resting on the flanks of a fourth insulating layer CI4 itself resting on the flanks of the second layer. insulating Cl2. The regions provided for siliciding include the G-gate regions, the source and drain raised regions RSn and RSp of the NMOS transistors TN and PMOS TP and the region 6 of the semiconductor film 20n located adjacent to the insulating side layers (IC1, FIG. Cl2, CI4 and CI5) and leaning on the flanks of the gate region G of the capacitor C (Figure 10). The siliciding process is then carried out in a conventional manner and known per se, by depositing a metal layer, for example a nickel-platinum alloy, on the structure of FIG. 10 and then by thermal annealing to form a silicide of metal, for example NiPtSi. Silicon zones ZSn and ZSp 5 are then obtained on the TN and TP transistors, a silicide zone ZSE1 on the gate G of the capacitor C and two silicided zones ZSE2 in the zone 6 of the semiconductor film. Since there was no epitaxy of semiconductor material on the zone 6 of the semiconductor film 20n of the capacitor C, the metal silicide ZSE2 formed in the zone 6 extends at least partially under the dielectric OX layer of the capacitor C In a case of a short grid, for example less than 20 nm, it is possible to carry out siliciding which extends completely under said dielectric layer OX.
    [0013] In addition, the gate regions G may be fully silicided ("fully silicied gate"), known per se to those skilled in the art. As a result, the capacitor C comprises a first electrode region E1 obtained by at least partial siliciding ZSE1 of the insulated gate region and a second electrode region E2 obtained by silicidation ZSE2 of the region 6 of the semiconductor film 20n. capacitor C. The silicided zones ZSE2 extend at least partially through the dielectric layer OX. As a result, the resistance between the two metal electrode regions of the capacitor C can be reduced so as to de facto decrease the voltage, the breakdown time, as well as the read voltage of the memory cell, especially in the case of a memory cell programmed with capacitor C slammed ,.
    权利要求:
    Claims (7)
    [0001]
    REVENDICATIONS1. A method, comprising an embodiment of at least one single programming type memory cell, comprising an embodiment of a MOS capacitor (C) in and / or on a semiconductor film (10) of a silicon on insulator substrate including a formation of a first electrode region (El) by at least partial siliciding (ZSE1) of an isolated gate region (G) resting on the semiconductor film (20n) and flanked by an insulating lateral region (CI1, Cl2, Cl4 and Cl5), and formation of a second electrode region (E2) by siliciding (ZSE2) of a region (6) of the semiconductor film (20n) located adjacent to said insulating side region (Cl1, Cl2, CI4 and CI5) without first proceeding to an epitaxy of semiconductor material on said region (6) of the semiconductor film.
    [0002]
    2. The method of claim 1, further comprising an embodiment of at least one MOS transistor (TN) whose formation of the source and drain regions comprises an epitaxy of a semiconductor material on the semiconductor film (20n), and wherein formation of said second electrode region (E2) comprises shielding said semiconductor film region (6) with at least one insulating layer (1) during said source and drain region (RSn) epitaxy.
    [0003]
    3. Method according to one of the preceding claims, wherein the substrate (10) is of the totally deserted silicon type insulator.
    [0004]
    An integrated circuit comprising a silicon-on-insulator substrate (10) having a semiconductor film (20n, p) located above a buried insulating layer (30), at least one single-programming type memory cell having a MOS capacitor (C) having a first electrode region (E1) including an at least partially silicided grid region (G) (ZSE1) and flanked by an insulating lateral region (CI1, Cl2, CI4 and CI5), a layer dielectric (OX) located between the gate region (G) and the semiconductor film (20n and 20p), and a second electrode region (E2) including a silicide region (ZSE2) of the semiconductor film adjacent to said insulating lateral region (CI1, C12, C14 and C15), and extending at least partially under the dielectric layer (OX).
    [0005]
    The integrated circuit of claim 4, wherein said silicide region (ZSE2) of the semiconductor film extends completely beneath said dielectric layer (OX).
    [0006]
    The integrated circuit of claim 4 or 5, further comprising at least one MOS transistor (TN or TP) having raised source and drain regions (RSn or RSp). 10
    [0007]
    7. Integrated circuit according to one of claims 4 to 6, wherein the substrate (10) is of the totally deserted silicon type insulator. 15
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    同族专利:
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    FR3036530B1|2015-05-19|2018-03-02|Stmicroelectronics Sa|METHOD FOR MAKING SINGLE PROGRAMMING MEMORY CELLS COMPRISING MOS CAPACITORS AND CORRESPONDING INTEGRATED CIRCUIT|US20150262291A1|2014-03-17|2015-09-17|Comenity Llc|Apply and buy with a co-branded virtual card|
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    法律状态:
    2016-04-21| PLFP| Fee payment|Year of fee payment: 2 |
    2016-11-25| PLSC| Publication of the preliminary search report|Effective date: 20161125 |
    2017-04-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-04-23| PLFP| Fee payment|Year of fee payment: 4 |
    2019-04-19| PLFP| Fee payment|Year of fee payment: 5 |
    2020-04-22| PLFP| Fee payment|Year of fee payment: 6 |
    2022-02-11| ST| Notification of lapse|Effective date: 20220105 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1554457|2015-05-19|
    FR1554457A|FR3036530B1|2015-05-19|2015-05-19|METHOD FOR MAKING SINGLE PROGRAMMING MEMORY CELLS COMPRISING MOS CAPACITORS AND CORRESPONDING INTEGRATED CIRCUIT|FR1554457A| FR3036530B1|2015-05-19|2015-05-19|METHOD FOR MAKING SINGLE PROGRAMMING MEMORY CELLS COMPRISING MOS CAPACITORS AND CORRESPONDING INTEGRATED CIRCUIT|
    CN201510831353.0A| CN106169474B|2015-05-19|2015-11-25|For manufacture include MOS capacitor One Time Programmable type memory cell method and corresponding integrated circuit|
    CN201520951130.3U| CN205140992U|2015-05-19|2015-11-25|Integrated circuit|
    US14/952,662| US9589968B2|2015-05-19|2015-11-25|Method for producing one-time-programmable memory cells and corresponding integrated circuit|
    US15/413,497| US9881928B2|2015-05-19|2017-01-24|Method for producing one-time-programmable memory cells and corresponding integrated circuit|
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